Field of the Invention:
The invention relates to a method for producing a polycrystalline silicon structure with a defined grain size on a semiconductor substrate.
In the production of integrated circuits, there is a frequent need for polycrystalline silicon structures, specifically as electric connections between circuit elements in particular, and as the circuit elements (for example capacitor electrodes) themselves. In that case, the crystal structure of the polysilicon is an important property. For example, it influences electric conductivity, diffusion of contaminants, the ability to structure narrow conductor tracks and adhesive properties, etc. . Details thereon are described in a book by Widmann, Mader and Friedrich, entitled "Techologie hochintegrierter Schaltungen" [Technology of Large-Scale Integrated Circuits], Chapter 3.8, Springer Verlag 1996, or in a book by Wolf and Tauber, entitled "Silicon Processing", Vol. 1, Chapter 6, Lattice Press 1987. In general, it is only polysilicon layers having a largely constant grain size or a narrow grain size distribution which can be used in semiconductor technology.
Polysilicon layers are usually produced by a CVD process such as is described, for example, in the reference by Widmann et al cited above. The mean grain size and the grain size distribution can be controlled by the temperature budget (temperature and time), and doping with boron, phosphorous, arsenic or similar materials, which is usually undertaken, also influences the grain size distribution which is achieved.
Doped polycrystalline silicon frequently constitutes the electric connection of a monocrystalline silicon region. An example thereof is a source region or drain region of a MOS transistor, or an emitter, base or collector of a bipolar transistor. The monocrystalline region in that case is mostly formed by a doped silicon region formed in the silicon substrate. The polycrystalline silicon structure forming the electric connection can be formed either from a polycrystalline silicon layer or from an amorphous silicon layer which becomes polycrystalline in later method steps.
In subsequent thermal steps, crystallization or recrystallization of the amorphous or polycrystalline silicon structure occurs. It is to be borne in mind in that case that the interface between the monocrystalline silicon region and the silicon structure mostly has a thin oxide, or can otherwise be contaminated or be of lower quality. That can lead to uncontrolled (re)crystallization, that is to say spatially strongly fluctuating grain sizes. The mechanical stress produced in the process can be reduced by the formation of crystal defects in the monocrystalline silicon such as, for example, the formation of dislocations. Those crystal defects worsen the electric properties of the substrate, for example by an increased leakage current. There Is therefore a risk that components or active structures disposed in the substrate (for example transistors, trench capacitors, pn junctions) do not have the prescribed electric properties, but already have incipient faults or medium term and long-term quality defects.
A first example of such a contact is the bit line contact in a DRAM memory, in which an arbitrary memory cell type is possible (for example a so-called stacked-cell or trench cell). A further example is the capacitor contact in such a cell, that is to say the contact between the memory electrode and the selection transistor. The problem occurs due to crystal defects, in particular in the case of memory cells having a trench capacitor, and is explained in detail in co-pending U.S. patent application Ser. No. 09/030,227, filed Feb. 25, 1998, entitled "Contact Between a Monocrystalline Silicon Region and a Polycrystalline Silicon Structure and Method For Producing Such a Contact" having the same inventors and the same filing date as the instant application